As chip capacities have continued to increase, programmable logic devices have increased both in their complexity and number of programmable logic components. In particular, programmable logic devices may now comprise one or more intellectual property cores (IP cores), which may be variously described as pre-packaged blocks of logic or macros.
As the complexity of IP cores has increased, so has the required investment in labor and finances needed to create them. Given their increased complexity, expense and value, some IP cores may now be licensed for only a limited duration, after which duration, rights to the IP may expire. For example, a given license may allow use of an IP core for only a limited duration, which duration may be less than the actual physical lifetime capability of the device.
One example of a typically known method of enforcing a time-limited license may be associated with enabling timed access to a given prototype kit of IP cores. A prototype version of various IP cores, from a given library for example, may be shipped to a prospective customer together with or as part of an embedded development evaluation kit. A counter block may be buried within the design kit embedded within the programmable logic device and used to time a sample period duration by counting to a predetermined value. Upon the counter reaching the value, control resources of the prototype device may disable elements of the core, placing them in an unusable state. The disablement might be performed, e.g., by isolating input and/or outputs of the device or by constantly holding it in a reset state. Accordingly, the sampled IP core may remain operational for only a limited time (typically a few hours), after which time, a reset might then be required for beginning a new trial period.